1. Field of the Invention
The present invention relates generally to methods for forming silicon oxide layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming sacrificial silicon oxide layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Indigenous in the art of microelectronic fabrication for forming microelectronic dielectric layers within microelectronic fabrications is the use of silicon oxide dielectric materials for forming silicon oxide microelectronic dielectric layers within microelectronic fabrications. Silicon oxide dielectric materials are desirable in the art of microelectronic fabrication for forming silicon oxide microelectronic dielectric layers within microelectronic fabrications insofar as silicon oxide dielectric materials are: (1) readily fabricated employing various conventional methods as are employed for forming microelectronic layers within microelectronic fabrications; and (2) possess desirable physical properties and electrical properties when formed into silicon oxide microelectronic dielectric layers employed within microelectronic fabrications.
While silicon oxide dielectric materials are thus clearly desirable in the art of microelectronic fabrication for forming silicon oxide microelectronic dielectric layers within microelectronic fabrications, silicon oxide dielectric materials, and the resulting silicon oxide microelectronic dielectric layers formed therefrom, are nonetheless not entirely without problems within the art of microelectronic fabrication. In that regard, it is known in the art of microelectronic fabrication that various methods for forming silicon oxide microelectronic dielectric layers within microelectronic fabrications provide detrimental effects upon microelectronic structures formed within the microelectronic fabrications within which are formed the silicon oxide microelectronic dielectric layers formed of the silicon oxide dielectric materials.
It is thus desirable in the art of microelectronic fabrication to provide methods which may be employed for forming, with desirable properties, silicon oxide microelectronic dielectric layers within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming silicon oxide microelectronic dielectric layers with desirable properties for various uses within microelectronic fabrications.
Included among the methods, but not limiting among the methods are those disclosed by: (1) Liu et al., in U.S. Pat. No. 5,151,381 (a two step thermal oxidizing method for forming a local oxidation of silicon (LOCOS) isolation region silicon oxide microelectronic dielectric layer within a semiconductor integrated circuit microelectronic fabrication with attenuated encroachment of a bird""s beak within an active region of a semiconductor substrate within which is formed the local oxidation of silicon (LOCOS) isolation region silicon oxide microelectronic dielectric layer within the semiconductor integrated circuit microelectronic fabrication); (2) Lojek et al., in U.S. Pat. No. 5,851,892 (a multi-step thermal oxidizing method for forming a gate dielectric layer or tunnel dielectric layer silicon oxide microelectronic dielectric layer within a semiconductor integrated circuit microelectronic fabrication with minimized inducted charge and/or maximized breakdown voltage within the gate dielectric layer or tunnel dielectric layer silicon oxide microelectronic dielectric layer within the semiconductor integrated circuit microelectronic fabrication); (3) Lin et al., in U.S. Pat. No. 6,057,208 (a chemical vapor deposition (CVD) method for forming a sacrificial dielectric layer, such as but not limited to a sacrificial silicon oxide microelectronic dielectric layer, with desirable etch properties within a semiconductor integrated circuit microelectronic fabrication such as to avoid over-etching a trench liner layer formed within an isolation trench adjoining the sacrificial dielectric layer when stripping from a semiconductor substrate upon which is formed the sacrificial dielectric layer and within which is formed the trench the sacrificial dielectric layer); and (4) Park et al., U.S. Pat. No. 6,107,143 (a thermal annealing method for forming within an isolation trench within a semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication a trench liner layer silicon oxide microelectronic dielectric layer having a lower etch rate than a trench filling layer silicon oxide microelectronic dielectric layer formed upon the trench liner layer silicon oxide microelectronic dielectric layer within the isolation trench employed within the semiconductor substrate employed within the semiconductor integrated circuit microelectronic fabrication).
Desirable in the art of microelectronic fabrication are additional methods which may be employed for forming within microelectronic fabrications silicon oxide microelectronic dielectric layers with desirable properties within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a silicon oxide layer.
A second object of the present invention is to provide a method for forming within the microelectronic fabrication the silicon oxide layer in accord with the first object of the present invention, wherein the silicon oxide layer is formed with desirable properties.
A third object of the present invention is to provide the method for forming within the microelectronic fabrication the silicon oxide layer in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming within a microelectronic fabrication a sacrificial silicon oxide layer.
To practice the method of the present invention, there is first provided a silicon semiconductor substrate. There is then thermally oxidized the silicon semiconductor substrate at a first temperature within a first oxidizing atmosphere to form a silicon oxide layer upon a partially consumed silicon semiconductor substrate formed from the silicon semiconductor substrate. There is then thermally oxidized the partially consumed silicon semiconductor substrate at a second temperature greater than the first temperature, and within a second oxidizing atmosphere, to form from the silicon oxide layer upon the partially consumed silicon semiconductor substrate a further oxidized silicon oxide layer upon a further consumed silicon semiconductor substrate. Finally, there is then stripped from the further consumed silicon semiconductor substrate the further oxidized silicon oxide layer, which comprises a sacrificial silicon oxide layer in accord with the present invention.
By employing for forming the sacrificial silicon oxide layer of the present invention the foregoing two step thermal oxidizing method which comprises: (1) a first thermal oxidizing step at a first temperature for forming from a silicon semiconductor substrate a silicon oxide layer formed upon a partially consumed silicon semiconductor substrate; and (2) a second thermal oxidizing step at a second temperature greater than the first temperature for forming from the silicon oxide layer upon the partially consumed silicon semiconductor substrate a further oxidized silicon oxide layer upon a further consumed silicon semiconductor substrate, where the further oxidized silicon oxide layer serves as the sacrificial silicon oxide layer, a microelectronic device formed within the further consumed silicon semiconductor substrate subsequent to stripping therefrom the further oxidized silicon oxide layer which serves as the sacrificial silicon oxide layer of the present invention may be formed with enhanced performance.
The present invention provides a method for forming within a microelectronic fabrication a silicon oxide layer, wherein the silicon oxide layer is formed with desirable properties.
The present invention realizes the foregoing objects by employing when forming a sacrificial silicon oxide layer in accord with the present invention a two step thermal oxidizing method which comprises: (1) a first thermal oxidizing step at a first temperature for forming from a silicon semiconductor substrate a silicon oxide layer formed upon a partially consumed silicon semiconductor substrate; and (2) a second thermal oxidizing step at a second temperature greater than the first temperature for forming from the silicon oxide layer upon the partially consumed silicon semiconductor substrate a further oxidized silicon oxide layer upon a further consumed silicon semiconductor substrate, where the further oxidized silicon oxide layer serves as the sacrificial silicon oxide layer. Within the present invention, a microelectronic device formed within the further consumed silicon semiconductor substrate subsequent to stripping therefrom the further oxidized silicon oxide layer which serves as the sacrificial silicon oxide layer of the present invention may be formed with enhanced performance, to thus provide within the context of the present invention the silicon oxide layer formed with desirable, and enhanced, properties.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, and in particular known in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process ordering and specific process limitations to provide the present invention. Since it is thus a specific process ordering and specific process limitations which provide at least in part the present invention, rather than the existence of methods and materials which provide the present invention, the method of the present invention is readily commercially implemented.